TOP 5 REQUIRED SKILLS:

• 2+ years of ASIC design, verification or related work experience
• Strong UVM, System Verilog Skills
• 2+ years experience with scripting tools and programming languages
• Quick understanding of Specs and Standards and developing relevant and thorough test plans
• Candidates should be comfortable checking builds, navigating test benches, analyzing coverage, and adding or enabling extra debug

TECHNOLOGIES:

• ASIC IP Verification
• UVM Development
• Bus protocols – AHB/AXI
• PERL
• Python

REQUIRED EDUCATION:

• Bachelor’s Degree of Science in Computer or Electrical Engineering, Computer Science or a related field (Looking at Computer and Electrical fields)

REQUIRED YEARS OF EXPERIENCE:

• 4 - 8 Years

PHYSICAL REQUIREMENTS:

• Frequently transports between offices, buildings and campuses up to ½ mile
• Frequently transports and installs equipment up to 5 lbs
• Performs required tasks at various heights (e.g.,standing or sitting)
• Monitors and utilizes computers and test equipment for more than 6 hours a day
• Continuous communication which includes the comprehension of information with colleagues,
• customers and vendors both in person and remotely

KEY WORDS:

• ASIC IP Verification
• UVM
• System Verilog
• PERL
• Python
• AHB
• AXI

JOB DESCRIPTION:

As a member of this team, your responsibilities will include:

• Work closely with design, architects and verification leads to develop the IP verification strategy and testplan.
• Create verification environment using UVM/System Verilog.
• Resolve architecture, design or verification problems by applying sound ASIC engineering practices.
• Write tests and regressions to identify any bugs.
• Develop functional coverage model, assertion checkers and scoreboards.
• Interpret the results of performance checks and identify issues.
• Communicate directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner.
• Perform RTL code coverage, assertion coverage, functional coverage analysis and gate level simulations
• Identify opportunities for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements.