About the Role:

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis, formal verification, Gate level functional & timing ECO in advanced technology nodes
• Develop & document STA & Synthesis strategies. Interact with methodology teams to address challenges related to new technology nodes.
• Familiar with constraint checking tools and techniques to deliver quality constraints for both pre and post CTS views.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Proficiency in advanced synthesis & STA techniques to achieve aggressive low power, area, and timing goals. Must be able to drive solutions for complex timing closure scenarios.
• Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms
• Experience with multi-clock and multi-power domain designs.
• Proficiency with ECO for functional and DFT timing closure
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science
  4-12 years’ experience
• RTL2Gate experience on advanced technology nodes (7nm and below)
• Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
• Experience in Block-level and Full-chip integration.
• Experience with Python, TCL, or Perl programming.
• Experience working with EDA tools like DC/Genus, ICC2/Innovus, Primetime

Preferred Qualifications:

• Experience in running physical-aware logic synthesis and achieving
• optimal synthesis QoR on low power designs
• Knowledge of static timing analysis, defining timing constraints and exceptions, corners/voltage definitions
• Experience with Python, TCL or Perl programming

Pay Range - $50/hr - $60/hr