Title – Hardware Engineer/ CAD Engineer

Duration – Six months with possible extension

Location – Remote

Pay range - $55-$60/hr.

Responsibility-

• Physical Design / EDA engineering role focused on Place & Route (PnR) and Design-Technology Co-Optimization (DTCO) in semiconductor chip development.
• Build and customize chip layout flows adapting standard Place & Route processes to explore better performance, power, and area tradeoffs with new process technologies
• Modify core PnR infrastructure tuning libraries, tech files, and tool settings so designs work optimally with new nodes or device architectures.
• Automate runs and experiments writing scripts (mostly Tcl) to run large numbers of design experiments efficiently.
• Own and support PnR flows maintaining, validating, and distributing these flows to the DTCO team and ensuring everything works smoothly.
• This is a hands-on chip physical design infrastructure role, bridging EDA tools, silicon process tech, and design optimization usually found at advanced semiconductor companies (Intel, TSMC, AMD, NVIDIA, etc.).

The Company offers the following benefits for this position, subject to applicable eligibility requirements: medical insurance, dental insurance, vision insurance, 401(k) retirement plan, life insurance, long-term disability insurance, short-term disability insurance, paid parking/public transportation, paid time off, paid sick and safe time, hours of paid vacation time, weeks of paid parental leave, and paid holidays annually – as applicable.